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S3C7544/p7544 produc t overview 1- 1 1 product overview overview the S3C7544 single-chip cmos microcontroller is designed for high-performance using samsung's newest 4-bit cpu core, sam47 (samsung arrangeable microcontrollers). with a versatile 8-bit timer/counter and a d/a converter, the S3C7544 offers an excellent design solution for a wide variety of telecommunication applications. up to 17 pins of the 24-pin sdip package can be dedicated to i/o. four vectored interrupts provide fast response to internal and external events. in addition, the S3C7544?s advanced cmos technology has realized substantially lower power consumption with a wide operating voltage range ? all at a substantially lower cost. otp the S3C7544 microcontroller is also available in otp (one time programmable) version, s3p7544. s3p7544 microcontroller has an on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the s3p7544 is comparable to S3C7544, both in function and in pin configuration.
product overview s3 c7544/p7544 1- 2 features summary memory 512 4-bit ram 4096 8-bit rom i/o pins 17 pins i/o n-channel open-drain i/o: 8 pins 8-bit basic timer programmable interval timer watchdog timer interval 8-bit timer/counter programmable interval timer external event counter function timer/counter clock output to tclo0 pin buzzer output four frequency output to buz pin d/a converter 8-bit d/a converter interrupts two external interrupt vectors two internal interrupt vectors one quasi-interrupt memory-mapped i/o structure data memory bank 15 bit sequential carrier supports 16-bit serial data transfer in arbitrary format power-down modes idle mode (only cpu clock stops) stop m ode (system clock stops) oscillation sources crystal, or ceramic for system clock crystal, ceramic: 0.4?6.0 mhz cpu clock divider circuit (by 4, 8, or 64) instruction execution times 0.95, 1.91, and 15.3 m s at 4.19 mhz 0.67, 1.33, 10.7 m s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v (at 3 mhz) 2.7 v to 5.5 v (at 6 mhz) package types 24-pin sop-375 24-pin sdip-300
S3C7544/p7544 produc t overview 1 - 3 block diagram dao arithmetic logic unit interrupt control block stack pointer program counter program status word flags instruction decoder clock x in internal interrupts p4.0?p4.3 p5.0?p5.3 8-bit timer/ counter i/o port 4 i/o port 5 d/a converter reset 512 x 4-bit data memory basic timer x out int0, int1 buzzer p0.0/int0 p0.1/int1 p0.2/ks0 p0.3/ks1 i/o port 0 i/o port 1 p1.0/tcl0 p1.1/tclo0 p1.2/clo p1.3/buz i/o port 2 p2.0 4 k byte program memory watchdog timer figure 1-1. S3C7544 simplified block diagram
product overview s3 c7544/p7544 1- 4 pin assignments v ss x out x in test p0.0/int0 dao p0.1/int1 reset p0.2/ks0 p0.3/ks1 p1.0/tcl0 p1.1/tclo0 v dd p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p2.0 p1.3/buz p1.2/clo 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 S3C7544 24 sop-375 24 sdip-300 figure 1-2. S3C7544 pin assignment diagrams
S3C7544/p7544 produc t overview 1 - 5 pin descriptions table 1-1. S3C7544 pin descriptions pin name pin type description share pin p0.0 p0.1 p0.2 p0.3 i 4-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. int0 int1 ks0 ks1 p1.0 p1.1 p1.2 p1.3 i/o 4-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. tcl0 tclo0 clo buz p2.0 i/o 1-bit i/o port. 1- or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. ? p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o port. 1- or 4-bit read/write and test is possible. pins are individually configurable as input or output. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. the n-channel open drain or push-pull output can be selected by software (1-bit unit). ? int0 i/o external interrupts with rising/falling edge detection p0.0 int1 i/o external interrupts with rising/falling edge detection p0.1 ks0 ks1 i/o quasi-interrupt input with falling edge detection p0.2 p0.3 tcl0 i/o external clock input for timer/counter p1.0 tclo0 i/o timer/counter clock output p1.1 clo i/o cpu clock output p1.2 buz i/o 0.5, 1, 2, or 4 khz frequency output at 4.19 mhz for buzzer sound p1.3 dao o 8-bit d/a converter output ? v dd ? main power supply ? v ss ? ground ? reset i reset signal ? test i chip test input pin. hold gnd when the device is operating. ? x in , x out ? crystal, ceramic oscillator signal for system clock ?
product overview s3 c7544/p7544 1- 6 table 1-2. overview of S3C7544 pin data sdip pin numbers share pins i/o type reset value circuit type v ss ? ? ? ? x out , x in ? ? ? ? test ? i ? ? p0.0, p0.1 int0, int1 i/o input d-4 reset ? i ? b p0.2 p0.3 ks0 ks1 i/o input d-4 p1.0 p1.1 p1.2 p1.3 tcl0 tclo0 clo buz i/o input d-2 p2.0 ? i/o input d-2 dao ? o output ? p4.0?p4.3 ? i/o input e-2 p5.0?p5.3 ? i/o input e-2 v dd ? ? ? ?
S3C7544/p7544 produc t overview 1 - 7 pin circuit diagrams v dd p - c hannel in n - c hannel figure 1-3. pin circuit type a v dd pull-up resistor schmitt trigger in figure 1-4. pin circuit type b data output disable out v dd p - channel n - channel figure 1-5. pin circuit type c p-channel pull-up enable data output disable in/out v dd circuit type c figure 1-6. pin circuit type d-2
product overview s3c 7544/p7544 1- 8 p-channel pull-up enable data output disable in/out v dd circuit type c figure 1-7. pin circuit type d-4 resistor enable v dd pull-up resistor v dd data output disable in/out pne figure 1-8. pin circuit type e-2
S3C7544/p7544 electrical data 14- 1 14 electrical data overview in this section, S3C7544 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: standard electrical characteristics ? absolute maximum r atings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data reten tion supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3 c7544/p7544 14 - 2 table 14- 1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 3 5 output current low i ol one i/o port active + 30 (peak) ma + 15 (note) all i/o ports active + 100 (peak) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 p0 and reset 0.8 v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 all input pins except v ih2 ?v ih3 ? ? 0.3 v dd v v il2 p0 and reset 0.2 v dd v il3 x in and x out 0.1
S3C7544/p7544 electrical data 14- 3 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma v dd ? 1.0 ? ? v output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.4 v ol 2 v dd = 4.5v to 5.5 v i ol = 4 ma all out ports except ports 4, 5 2 v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.6 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a pull- u p resistor r l1 v dd = 5 v ; v i = 0 v except reset 25 45 100 k w v dd = 3 v 50 90 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 220 400 v dd = 3 v 200 450 800
electrical data s3 c7544/p7544 14 - 4 table 14- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.4 10.0 ma current (1) (dac on) crystal oscillator; c1 = c2 = 22pf 4.19mhz 2.7 8.0 i dd 2 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 2.3 8.0 ma (dac off) crystal oscillator; c1 = c2 = 22pf 4.19mhz 1.7 5.5 v dd = 3 v 10% 6.0mhz 1.1 4.0 4.19mhz 0.8 3.0 i dd 3 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.7 2.5 ma crystal oscillator; c1 = c2 = 22pf 4.19mhz 0.5 1.8 v dd = 3 v 10% 6.0mhz 0.3 1.5 4.19mhz 0.2 1.0 i dd 4 stop mode; v dd = 5.0 v 10% ? 0.2 3.0 m a stop mode; v dd = 3.0 v 10% 0.1 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include the current drawn through internal pull-up resistors. 2. i dd1 typical values are measured when dadata register value is 055h. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 0.7 5 mhz 15.625 khz cpu clock 3 mhz 6 mhz 400 khz main osc. freq. 1.5 mhz 1 2 2.7 3 4 5 6 7 1 .8 figure 14- 1. standard operating voltage range
S3C7544/p7544 electrical data 14- 5 table 14- 3. oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3 c7544/p7544 14 - 6 table 14-4 . recommended oscillator constants (t a = ? 40 c + 85 c , v dd = 1.8 v to 5 . 5 v) manufacturer series number (1) frequency range load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 14-5 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 14-6 . d/a converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3 . 5 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units resolution ? ? ? ? 8 bits absolute accuracy ? ? 3 ? 3 lsb differential linearity error dle ? 1 ? 1 lsb setup time t su ? ? 5 m s output resistance r o 4.5 5 5.5 k w
S3C7544/p7544 electrical data 14- 7 table 14-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 1.33 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih, t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth, t intl int0, int1, ks0?ks1 10 ? ? m s reset input low width t rsl input ? ? 10 m s table 14-8 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay the execution of cpu ins tructions during the wait time.
electrical data s3 c7544/p7544 14 - 8 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode ~ ~ ~ ~ figure 14-2. stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention stop mode t wait t srel idle mode normal operating mode power-down mode terminating (interrupt request) ~ ~ ~ ~ figure 14- 3. stop mode release timing when initiated b y interrupt request
S3C7544/p7544 electrical data 14- 9 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 14-5 . clock timing measurement at x in
electrical data s3 c7544/p7544 14 - 10 tcl t til t tih 0.7 v dd 0.3 v dd 1 / f ti figure 14- 6. tcl timing reset 0.2 v dd t rsl figure 14-7 . input timing for reset reset signal int0, 1 ks0 to ks1 t intl t inth 0.8 v dd 0.2 v dd figure 14- 8. input timing for external interrupts
S3C7544/p7544 mechanical data 15? 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table note : typical dimensions are in millimeters. 30-sdip-400 8.94 0.2 0.56 0.1 27.48 0.2 0 ~ 15 0.25 +0.1 ? 0.05 #1 15 30 16 10.16 (1.30) 1.12 0.1 1.778 0.51min 3.81 0.2 3.30 0.3 5.08max figure 15 - 1. 30-sdip-400 package dimensions
S3C7544/p7544 s3p75 44 otp 16- 1 16 s3p7544 otp overview the s3p7544 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C7544 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p7544 is fully compatible with the S3C7544, both in function and in pin configuration. because of its simple programming requirements, the s3p7544 is ideal for use as an evaluation chip for the S3C7544. v ss / v ss x out x in v p p / test p0.0/int0 dao p0.1/int1 reset reset / reset p0.2/ks0 p0.3/ks1 p1.0/tcl0 p1.1/tclo0 v dd / v dd p5.3/ sclk p5.2/ sdat p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p2.0 p1.3/buz p1.2/clo 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 s3p7544 24 sop-375 24 sdip-300 figure 16-1. s3p7544 pin assignments (24 sop-375, 24 sdip-300 package)
s3p7544 otp S3C7544 /p7544 16- 2 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p5.2 sdat 22 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p5.3 sclk 23 i/o serial clock pin. input only pin. test test 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) hold gnd when otp is operating. reset reset 8 i chip initialization v dd /v ss v dd /v ss 24/1 ? logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means the 32-sop otp pin number. table 16-2. comparison of s3p7544 and S3C7544 features characteristic s3p7544 S3C7544 program memory 4 k-byte eprom 4 k-byte mask rom operating voltage (v dd ) 1.8 v (3 mhz) to 5.5 v 1.8 v (3 mhz) to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 24 sop, 24 sdip 24 sop, 24 sdip eprom programmability user program one time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p7544, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3C7544/p7544 s3p75 44 otp 16- 3 otp electrical data table 16-4 . absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 3 5 output current low i ol one i/o port active + 30 (peak) ma + 15 (note) all i/o ports active + 100 (peak) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low (i ol ) are calculated as peak value duty . table 16-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 p0 and reset 0.8 v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 all input pins except v ih2 ?v ih3 ? ? 0.3 v dd v v il2 p0 and reset 0.2 v dd v il3 x in and x out 0.1
s3p7544 otp S3C7544 /p7544 16- 4 table 16-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma v dd ? 1.0 ? ? v output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.4 v ol 2 v dd = 4.5v to 5.5 v i ol = 4 ma all out ports except ports 4, 5 2 v dd = 1 . 8 v to 5.5 v i ol = 1.6 ma 0.6 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a pull- u p resistor r l1 v dd = 5 v ; v i = 0 v except reset 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
S3C7544/p7544 s3p75 44 otp 16- 5 table 16-5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.4 10.0 ma current (1) (dac on) crystal oscillator; c1 = c2 = 22pf 4.19mhz 2.7 8.0 i dd 2 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 2.3 8.0 ma (dac off) crystal oscillator; c1 = c2 = 22pf 4.19mhz 1.7 5.5 v dd = 3 v 10% 6.0mhz 1.1 4.0 4.19mhz 0.8 3.0 i dd 3 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.7 2.5 ma crystal oscillator; c1 = c2 = 22pf 4.19mhz 0.5 1.8 v dd = 3 v 10% 6.0mhz 0.3 1.5 4.19mhz 0.2 1.0 i dd 4 stop mode; v dd = 5.0 v 10% ? 0.2 3.0 m a stop mode; v dd = 3.0 v 10% 0.1 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include the current drawn through internal pull-up resistors. 2. i dd1 typical values are measured when dadata register value is 055h . cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 0.7 5 mhz 15.625 khz cpu clock 3 mhz 6 mhz 400 khz main osc. freq. 1.5 mhz 1 2 2.7 3 4 5 6 7 1 .8 figure 16-2 . standard operating voltage range
s3p7544 otp S3C7544 /p7544 16- 6 table 16-6 . oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
S3C7544/p7544 s3p75 44 otp 16- 7 table 16-7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 16-8 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3 . 5 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units resolution ? ? ? ? 8 bits absolute accuracy ? ? 3 ? 3 lsb differential linearity error dle ? 1 ? 1 lsb setup time t su ? ? 5 m s output resistance r o 4.5 5 5.5 k w table 16-9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 1.33 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih, t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 interrupt input high, low width t inth, t intl int0, int1, ks0?ks1 10 ? ? m s reset input low width t rsl input ? ? 10 m s
s3p7544 otp S3C7544 /p7544 16- 8 table 16-10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 /fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay the execution of cpu ins tructions during the wait time.

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